The present invention generally relates to improved semiconductor devices which use a graded band gap structure to promote the injection of holes or electrons at one interface of an insulator, while, simultaneously, electron or hole injection from the opposite interface is blocked and which use a trapping layer to capture holes or electrons with 100% efficiency. More particularly, the present invention, in a preferred embodiment, relates to a graded oxide metal-silicon dioxide-silicon (GOMOS) semiconductor structure which is useful in forming a more efficient memory function.
FET memory devices are known in the art. One such device employs a MI.sub.1 I.sub.2 S structure wherein I.sub.1 and I.sub.2 denote first and second insulator layers. The I.sub.1 I.sub.2 interface may include a metallic impurity which provides a well-defined electron trapping region. The presence or absence of trapped electrons in this region is used to define a memory function either by different values of capacitance of the structure or by monitoring the value of source-drain current as affected by the trapped electron charges in the presence of suitable applied gate voltages. Metallic impurities are not always required at the I.sub.1 I.sub.2 interface as the same effect can be realized by using two different kinds of insulators. For example, one such known device employs an MNOS structure where a thin oxide film is first formed on a silicon substrate, and over this thin oxide film is laid a much thicker silicon nitride film. In this structure, electrons or holes are trapped in the silicon nitride layer. There is a disadvantage associated with this particular structure, however, and that relates to the thin oxide layer. This oxide layer must be quite thin, on the order of about 20 A thick, in order to allow tunneling of the electrons or holes from the Si substrate. Reliability problems have been encountered with memory devices with this thin tunnel oxide layer because of the high fields across it during operation.
U.S. Pat. No. 4,104,675 and assigned to a common assignee discloses a device which uses a graded band gap structure to make a charge storage device wherein injection of holes or electrons from one contact is possible without simultaneous injection of electrons or holes from the other contact. The patent shows a structure employing the band gap reduction in an GOMOS FET which performs a memory function. The GOMOS structure employs hole trapping near the Si--SiO.sub.2 interface with the structure in an FET configuration. The "write" step involves hole injection from the gate electrode under moderate positive voltage bias and transport to the Si--SiO.sub.2 interface where some of the positively-charged holes are trapped in a very stable manner. The "erase" step involves electron injection from the gate electrode under moderate negative voltage bias and transport to the Si--SiO.sub.2 interface where the electrons would annihilate trapped holes very readily. The "read" operation uses the conductance of the silicon surface to sense the charge state of the oxide region near the Si--SiO.sub.2 interface and uses low gate voltages to prevent further charging of this region.
The band gap graded structure may be fabricated by forming several pyrolytic or CVD SiO.sub.2 layers over a relatively thick thermal SiO.sub.2 layer with the pyrolytic SiO.sub.2 layers having sequentially increasing excess Si content. The structure may also be fabricated by controlled Si ion implantation in the thermal SiO.sub.2 layer. The structure can also be fabricated using plasma deposited layers of SiO.sub.2 graded with Si. Other insulating layers which given enhanced carrier injection from the gate electrode due to actual band gap reduction or effective band gap reduction (for instance, by trap assisted tunneling) are also possible.
The devices having the structure shown in U.S. Pat. No. 4,104,675 have the disadvantages of having the charge trapping region being process dependent, suffer from surface state build-up at the Si--SiO.sub.2 interface due to the passage of holes, are sensitive to "hot" carrier injection from the Si substrate due to the presence of the trapped holes, and require hole injection and trapping to be the first operation since these traps do not capture electrons without the presence of the holes first.